Application Deployment Featured Article

Intel Microprocessors Improve Operations of Deployed Deep Packet Inspection Appliances

 
February 08, 2013

 


Intel’s (News - Alert) new Xeon E3 and E5 series microprocessors – which are known as “Sandy Bridge” – are improving the overall functionality of newly deployed deep packet inspection appliances.


The E3 and E5 up CPU processing, memory, and I/O performance, according to a recent report from Jeff Hudgins (News - Alert), vice president of Marketing and Customer Program Management at NEI. They also lessen the number of bottlenecks, and improve the handling of DPI algorithms. It’s a clear improvement over legacy offerings.

“General-purpose microprocessors have traditionally served within the control plane of communications and networking equipment, leaving ASICs, FPGAs and various accelerator cards to handle packet processing in the data plane,” Hudgins commented in a blog post. “Intel’s faster and more efficient Xeon E3/E5 processors are better equipped to handle deep packet inspection security algorithms and will replace many of the network processors commonly used in today’s enterprise- and carrier-class servers.”

Additionally, the robust technology provides up to 17 percent more CPU performance compared to the older Lynnfield 45 nm quad-core Xeon X34xx processors. The Xeon E3 and E5 provide up to 60 percent more performance and 30 percent more energy efficiency compared to the older version as well.

In a related matter, Austin Hipes, vice president of Technology at NEI (News - Alert), said in a recent TMCnet article that deep packet inspection, data compression and decompression, and encryption take place at higher throughput rates with the Intel platform for communications infrastructure.

It is made up of multi-core processors in combination with Intel QuickAssist technology hardware accelerators, according to TMCnet.

“As a result, the platform enhances DPI capabilities by processing over 160 million packets of data per second as compared to NPU’s 100 million packets per second,” TMCnet’s Ashok Bindra explained. “The elimination of NPUs in the hardware scheme along with the faster processing capacity and reduced development time needed for new applications results in substantial cost reductions for the OEM. Further, the high performance nature of the new platform is attributed to Intel Xeon processors (E5-2600 series) arranged in a dual-socket configuration. It can be configured to provide up to 16 cores, an 80 channel root complex of PCI (News - Alert) Express (PCIe) Gen 3.0 and 8 1600 MHz memory controllers.”

Moreoer, hardware accelerators take away encryption and data compression from the main CPU load. The CPU is now “free to do other work.”

“With the cores freed from encryption duties, they can now perform DPI and application processing tasks, effectively working on both the control and data planes simultaneously,” Hipes added.




Edited by Jamie Epstein
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